Phase-Locked Loop Design for Grid-Connected Converters under unbalanced grid Conditions

Abstract

The purpose of this master project is to investigate different phase locked loop (PLLs) architectures for grid-voltage synchronization under different kinds of grid conditions such as frequency and magnitude variations. After introducing PLL basics, we presented different convention PLL methods used for grid-synchronization (single as well as three phase systems). For the case of three phase systems, we investigated the difference between the following methods: i) abc-frame PLL, ii) αβ-PLL and, iii) dqframe PLL, and how one can design the controller parameters. Despite the fact that these methods work well under frequency and amplitude variations of the grid voltages, they are sensible to phase shift disturbances and distorted signals. The last part of this report is dedicated to an advanced PLL structure, known as decoupled double synchronous reference frame PLL (DDSRF-PLL). Simulation results show that the PLL in question guarantee better performance compared to conventional methods with respect to phase shift variations.